1. Field of the Invention
The present invention generally relates to a reading operation of reading memory cell information in a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device provided with a read-out circuit for reading multi-level information held in memory cells at high speed.
2. Description of the Related Art
In a nonvolatile semiconductor memory device, such as a flash memory, memory cell information is stored by using the current drive capacity of a nonvolatile transistor in a nonvolatile memory cell. That is, the memory cell information (i.e., data) of “1” or “0” is stored in the nonvolatile transistor depending on whether or not the nonvolatile transistor conducts current, or depending on whether the nonvolatile transistor conducts an increased current or a decreased current.
In recent years, a method of storing 2-bit data in one memory cell has been introduced in nonvolatile semiconductor memory devices, in order to increase recording density. In such a method, the potential held by one memory cell is divided into four states: “1”, “⅔”, “⅓”, and “0”.
For example, the information held by each memory cell is represented by the value of 2 bits in which the data “11”, “10”, “01”, and “00” are assigned to the memory cell potentials “1”, “⅔”, “⅓”, and “0”, respectively.
FIG. 1 shows the composition of a conventional nonvolatile semiconductor memory device in which each memory cell holds binary data.
A memory core portion 1 includes a plurality of nonvolatile memory cells 10 (memory cell array), which are connected in a 2-dimensional matrix formation by word lines WL and bit lines BL, a decoder 11 to which an address signal is inputted, a column selector (YSEL) 12, a sector switch (SECY) 13, and a sector switch (SECY) 14.
In a nonvolatile semiconductor memory device, the read-out circuit (the sense circuit portion) compares a read-out current on a global bit line or a line connected to a selected memory cell, with a reference current from a reference cell to determine whether the data read is “1” or “0”.
In the nonvolatile semiconductor memory device of FIG. 1, each memory cell 10 stores and holds binary data of “1” or “0”. During a data read-out operation a level of a current IGBL flowing on a global bit line GBL, which is connected to a bit line BL of a memory cell 10 selected in accordance with an address signal (Address), is supplied to a first cascode circuit (CASCOD) 31 via a data bus line LDB. The cascode circuit 31 converts the received data read-out current IGBL into a voltage signal, and outputs the voltage signal to a first input of a differential amplifier (SAMP) 30.
A reference cell (RC) 20 is provided outside the memory core portion 1. The reference cell 20 is a memory cell for supplying a reference current IREF to the differential amplifier 30. The reference current IREF is set to an intermediate value between the current flowing through the global bit line GBL when the data held by the selected memory cell 10 is “1” and the current flowing through the global bit line GBL when the data held by the selected memory cell 10 is “0”.
The reference current IREF from the reference cell (RC) 20 is supplied to a second cascode circuit (CASCOD) 32 via a reference bus line to which the reference cell (RC) 20 is connected. The cascode circuit 32 converts the received reference current IREF into a voltage signal, and outputs the voltage signal to a second input of the differential amplifier 30.
The differential amplifier 30 judges whether the data read-out of the selected memory cell 10 is a “1” or “0” by comparing the voltage level of the memory cell current IGBL at the time of the data read-out with the voltage level of the reference current IREF.
In the nonvolatile semiconductor memory device of FIG. 1, the global bit line GBL is connected with the plurality of bit lines BL of the memory core portion 1 through the sector switch 13. The nonvolatile semiconductor memory device has a hierarchical structure. The global bit line GBL is inputted into the column selector 12 for every predetermined number of bit lines. One of the bit lines is selected by the column selector 12, and the global bit line GBL is connected to the data bus line LDB by the selected bit line.
In the nonvolatile semiconductor memory device of FIG. 1, the memory cell 10 and the reference cell 20 are provided on opposite sides of the differential amplifier 30. An unbalance in capacity of parasitic elements in the sector switch 13, the sector switch 14 and the column selector 12 provided on the side of the memory core portion 1 iscorrected by a load capacitor CLD1 provided in the current path of the reference cell 20, and a load capacitor CLD2 provided between the cascode circuit 31 provided on the side of the memory cell 10 and the differential amplifier 30.
In a case of a nonvolatile semiconductor memory device in which each memory cell holds four-level data, during a read operation, a selected memory cell current at the time of the data read-out is compared with each of the three different reference-current values to determine a value of the read-out data. The three reference-current potential values are: the potential “¾” which is the intermediate potential value of “1” and “⅔”, the potential “½” which is the intermediate potential value of “⅔” and “⅓”, and the potential “¼” which is the intermediate potential value of “⅓” and “0”.
FIG. 2 shows the composition of conventional nonvolatile semiconductor memory device in which each memory cell holds four-level data. FIG. 3 is a waveform diagram for explaining operation of a data bus line at a time of a read-out operation in the nonvolatile semiconductor memory device of FIG. 2.
The memory device of FIG. 2 is similar to that of FIG. 1 and like reference numerals in FIGS. 1 and 2 refer to like elements. The description of like elements is not repeated. Similar to in the memory device of FIG. 1, in the nonvolatile semiconductor memory device of FIG. 2, the read-out circuit (sense circuit portion) compares the read-out current flowing on the global bit line GBL or the bit line BL connected to a selected memory cell 10, with a reference current from a reference cell to determine whether the read-out data is “1” or “0”.
However, the conventional nonvolatile semiconductor memory device of FIG. 2 includes three different reference cells 21 (RC1), 22 (RC2) and 23 (RC3), and a selector switch 24. Shown in FIG. 2, in a case in which the data held by each memory cell is four-level data, one of the three different reference cells: the reference cell 21 (RC1) supplying the reference current corresponding to the intermediate potential “¾”, the reference cell 22 (RC2) supplying the reference current corresponding to the intermediate potential “½”, and the reference cell 23 (RC3) supplying the reference current corresponding to the intermediate potential “¼” is selected by the selector switch 24, and a read-out current is compared with the reference current from the selected reference cell. Then, it is determined whether the potential held by the memory cell concerned is any of “1”, “⅔”, “⅓”, or “0”.
Moreover, similar to the composition of FIG. 1, in order to correct an unbalance of capacity of parasitic elements, the load capacitor CLD2 is provided between the cascode circuit 31 on the side of the memory cell 10 and the differential amplifier 30, and load capacitors CLD11, CLD12 and CLD13 are respectively provided in the current paths of the reference cells 21, 22 and 23.
The reference cells 21–23 are arranged at external positions different from the memory cell array where the respective memory cells 10 are arranged, in order to avoid the stress of a writing or erasing operation to the memory cells 10.
For this reason, in order to correct parasitic resistances and junction capacitances of the column selector 12 and the sector switches 13 and 14 existing on the side of the memory cell array, and parasitic components of the adjoining non-selected bit lines BL and the global bit lines GBL, and the data bus lines LDB, the load capacitors CLD11, CLD12, and CLD13 are connected to reference bus lines to which the reference cells 21, 22, and 23 are connected, respectively. By adding such load capacitors, the transient response characteristics of the reference bus line and the data bus line on the side of the memory cell are made equivalent, and a decrease in the sense time of the differential amplifier 30 may be achieved.
As described above, in the conventional nonvolatile semiconductor memory device of FIG. 2, the provision of the load capacitors CLD11, CLD12, and CLD13 in the current paths on the side of the reference cells artificially “balance” the capacity characteristics of the parasitic elements in the memory-cell-side current paths from the memory cells 10 to the differential amplifier 30.
However, the capacity of the parasitic elements in the current paths on the side of the memory cells varies with a distribution width caused by manufacturing tolerance. That is, the variations in the etching process of each wiring may cause the variation in the intervals of the adjoining wires, and the capacity of the parasitic elements having the intervals of the adjoining wires varies with a width in the distribution.
Moreover, variations in thickness of interlayer insulation films may cause variations in the intervals of upper and lower layer wirings. The capacity of the parasitic elements having the intervals of the adjoining wires varies with a certain width in the distribution. Furthermore, junction capacitance and an “ON” resistance may also vary with a certain width in the distribution and by variations of parameters of the transistors, such as a gate oxide film, and a concentration and depth of a diffusion layer.
In addition, a die size of a chip tends to be enlarged in connection with a larger capacity of a nonvolatile semiconductor memory device. Therefore, a difference in the on-chip parasitic capacitance in the same chip tends to be large. Simultaneously, the use of larger-diameter wafers may cause difference within the wafer surface to also become large.
Strictly speaking, the current path formed from the memory cells arranged in the sector through the bit lines having the hierarchical structure, and the reference-current path directly linked from the reference cells arranged in the external region have the different physical parameters in and around a position where the bit line is arranged, or the current path is formed.
For this reason, even if, in the design stage, the load capacitors CLD1, CLD2, and CLD3 which are suited to the characteristics of both the parasitic components are added, manufacturing variations and in-surface differences in the chip or wafer are different for each product. Thus, it is difficult to make the characteristics of the reference cells conform with the characteristics of the parasitic components in a conventional nonvolatile semiconductor memory device.
FIG. 4A is a waveform diagram for explaining read-out operation of the conventional nonvolatile semiconductor memory device. As shown in FIG. 4A, in the conventional nonvolatile semiconductor memory device, the potential change in the current path (data bus voltage) on the side of the memory cells and the potential change in the current path (reference voltage) on the side of the reference cells in the transient state of the read-out operation are not in agreement due to the propagation delay of the signal by the parasitic components.
When the timing of detection of the memory cell information is moved in advance before the time the potential change is completed within the predetermined limits, there is the possibility that the memory cell information is incorrectly detected. To avoid incorrect detection, it is necessary to delay the timing of detection of the memory cell information until the potential change is completed within the predetermined limits. This becomes a hindrance to performing the read-out operation at a higher speed.